The present invention relates to integrated circuits, and more specifically, to multi-layered ceramic packages. The packages are usually used for mounting or supporting semiconductor chips or modules. A typical semiconductor chip includes miniaturized semiconductor devices formed on a semiconductor substrate. The semiconductor substrate, such as silicon, is usually brittle, and relies on the carrier, on which it is mounted, for support and mechanical rigidity. In addition, to providing support, the carrier provides a mechanical and an electrical interfaces between the chip and the device, such as a printed circuit board (PCB) or the like, on which the chip/carrier combination is mounted. The combination is termed a “chip carrier” or “chip package”, which can be a single-chip module (SCM) or multi-chip modules (MCM).
A multi-layered ceramic package is attractive for interfacing SCM or MCM to a Printed Circuit Board (PCB) or the like; because it can provide very high wiring and power densities. The densities are hallmarks of an efficient, and high performance system. A conventional ceramic package is usually formed from a plurality of signal planes carrying electrical conductors, and sandwich between a plurality of reference planes. Each signal plane is placed between upper and lower reference planes which provide supply (Vdd) and ground (gnd) potential to the signal plane. Each reference plane is, usually, a grid structure, which is formed from intersecting reference lines accessible by vias. The grid structure may be fabricated on a ceramic substrate.
To meet performance requirements, imposed by high performance systems, there has been a steady increase in the number of signal lines and signal speed provided in a chip package. As the speed and number of signal lines increase, the potential for cross-talk between signal lines in the same layer, and signal lines in adjacent layers, also, increase. The cross-talk results in the creation of electrical noise, which adversely affects the signaling rates and performance in a chip package.